Spectrum Efficiency and Processing Latency Trade-offs in Panel-Based LIS

TL;DR

This paper explores the balance between spectral efficiency and processing latency in large intelligent surface systems, analyzing antenna distribution and detection algorithms through hardware-based latency modeling and simulations.

Contribution

It introduces a latency model based on FPGA and ASIP hardware results and evaluates the impact of antenna distribution and detection algorithms on latency and efficiency.

Findings

Distributing antennas improves reliability with limited latency impact.

Switching to MRC detection reduces latency significantly.

A latency model based on real hardware implementation results.

Abstract

The next generation wireless systems will face stringent new requirements, including ultra-low latency, high data rates and enhanced reliability. Large Intelligent Surfaces, is one proposed solution that has the potential to solve these high demands. The real-life deployment of such systems involves different design considerations with non-trivial trade-offs. This paper investigates the trade-off between spectral efficiency and processing latency, considering different antenna distribution schemes and detection algorithms. A latency model for the physical layer processing has been developed, using real FPGA and application-specific instruction processor (ASIP) hardware implementation results. Simulation results using an indoor environment show that distributing antennas throughout the scenario improves overall reliability, while the impact from this on latency is limited both when using zero-forcing (ZF) and Minimum Mean Square Error (MMSE) detection. Changing the detection algorithm to maximum-ratio combining (MRC) from ZF or MMSE, however, reduces the latency significantly, even if a larger number of antennas are needed to achieve a similar spectrum efficiency.