A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors

TL;DR

This paper investigates reducing the cell ratio in 65-nm CMOS SRAM cells to minimize area and power, analyzing stability impacts and proposing solutions to maintain performance while achieving significant benefits.

Contribution

It demonstrates that lowering the cell ratio to 1 in 65-nm CMOS SRAMs reduces area and leakage, improves energy efficiency, and enhances layout regularity, with methods to mitigate stability issues.

Findings

25% cell area reduction compared to ratio 2

35% leakage current decrease

30% improvement in soft error rate

Abstract

As minimum area SRAM bit-cells are obtained when using cell ratio and pull-up ratio of 1, we analyze the possibility of decreasing the cell ratio from the conventional values comprised between 1.5-2.5 to 1. The impact of this option on area, power, performance and stability is analyzed showing that the most affected parameter is read stability, although this impact can be overcome using some of the read assist circuits proposed in the literature. The main benefits are layout regularity enhancement, with its consequent higher tolerance to variability, cell area reduction by 25% (with respect to a cell having a cell ratio of 2), leakage current improvement by a 35%, as well as energy dissipation reduction and a soft error rate per bit improvement of around 30%.