High-Level Surface Code Decoding via Parallel FFNNs on CIM Platforms

TL;DR

This paper introduces a parallel FFNN-based high-level surface code decoder optimized for CIM hardware, achieving faster decoding with higher thresholds than traditional methods, crucial for scalable quantum error correction.

Contribution

The paper proposes a novel parallel FFNN decoder for surface codes and evaluates its performance on CIM hardware, demonstrating improved speed and thresholds over existing serial neural decoders.

Findings

Decoding threshold of 14.22%, surpassing MWPM's 10.3%

Achieved decoding latencies below 250 ns for multiple code distances

Hardware simulation indicates feasibility in cryogenic quantum environments

Abstract

Due to the high sensitivity of qubits to environmental noise, which leads to decoherence and information loss, active quantum error correction(QEC) is essential. Surface codes represent one of the most promising fault-tolerant QEC schemes, but they require decoders that are accurate, fast, and scalable to large-scale quantum platforms. In all types of decoders, fully neural network-based high-level decoders offer decoding thresholds that surpass baseline decoder-Minimum Weight Perfect Matching (MWPM), and exhibit strong scalability, making them one of the ideal solutions for addressing surface code challenges. However, current fully neural network-based high-level decoders can only operate serially and do not meet the current latency requirements (below 440 ns). To address these challenges, we first propose a parallel fully feedforward neural network (FFNN) high-level surface code decoder, and comprehensively measure its decoding performance on a computing-in-memory (CIM) hardware simulation platform. With the currently available hardware specifications, our work achieves a decoding threshold of 14.22%, surpassing the MWPM baseline of 10.3%, and achieves high pseudo-thresholds of 10.4%, 11.3%, 12%, and 11.6% with decoding latencies of 197.03 ns, 234.87 ns, 243.73 ns, and 251.65 ns for distances of 3, 5, 7 and 9, respectively. The impact of hardware parameters and non-idealities on these results is discussed, and the hardware simulation results are extrapolated to a 4K quantum cryogenic environment.