Reconfigurable Stream Network Architecture

TL;DR

This paper introduces the Reconfigurable Stream Network Architecture (RSN), an ISA abstraction for heterogeneous AI hardware that improves efficiency, reduces latency, and enhances throughput by modeling data paths as circuit-switched networks.

Contribution

The paper presents a novel ISA abstraction called RSN for DNNs, enabling efficient coordination of heterogeneous resources and phase transitions with explicit control over data movement.

Findings

Reduces latency by 6.1x on a heterogeneous platform

Improves throughput by 2.4x to 3.2x compared to state-of-the-art

Achieves 2.1x higher energy efficiency than A100 GPU

Abstract

As AI systems grow increasingly specialized and complex, managing hardware heterogeneity becomes a pressing challenge. How can we efficiently coordinate and synchronize heterogeneous hardware resources to achieve high utilization? How can we minimize the friction of transitioning between diverse computation phases, reducing costly stalls from initialization, pipeline setup, or drain? Our insight is that a network abstraction at the ISA level naturally unifies heterogeneous resource orchestration and phase transitions. This paper presents a Reconfigurable Stream Network Architecture (RSN), a novel ISA abstraction designed for the DNN domain. RSN models the datapath as a circuit-switched network with stateful functional units as nodes and data streaming on the edges. Programming a computation corresponds to triggering a path. Software is explicitly exposed to the compute and communication latency of each functional unit, enabling precise control over data movement for optimizations such as compute-communication overlap and layer fusion. As nodes in a network naturally differ, the RSN abstraction can efficiently virtualize heterogeneous hardware resources by separating control from the data plane, enabling low instruction-level intervention. We build a proof-of-concept design RSN-XNN on VCK190, a heterogeneous platform with FPGA fabric and AI engines. Compared to the SOTA solution on this platform, it reduces latency by 6.1x and improves throughput by 2.4x-3.2x. Compared to the T4 GPU with the same FP32 performance, it matches latency with only 18% of the memory bandwidth. Compared to the A100 GPU at the same 7nm process node, it achieves 2.1x higher energy efficiency in FP32.