Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment

TL;DR

This study experimentally characterizes the susceptibility of 65 nm CMOS 6T and 8T SRAM cells to cosmic-ray-induced single event upsets at ground level, revealing differences in cross-section and multi-bit event trends.

Contribution

It provides the first experimental ground-level cosmic-ray irradiation data for 65 nm CMOS SRAM cells, comparing 6T and 8T designs under accelerated testing conditions.

Findings

6T cells have 1.45 times higher SEU cross-section than 8T cells.

Multi-bit event occurrence is higher in 6T cells.

SRAM memories are suitable as radiation monitors in high-energy physics.

Abstract

We present experimental results of the cross-section related to cosmic-ray irradiation at ground level for minimum-sized six-transistors (6T) and eight-transistors (8T) bit-cells SRAM memories implemented on a 65 nm CMOS standard technology. Results were obtained from accelerated irradiation tests performed in the mixed-field irradiation facility of the CERN High-energy Accelerator test facility (CHARM) at the European Organization for Nuclear Research in Geneva, Switzerland. A 1.45x higher SEU cross-section was observed for 6T-cell designs despite the larger area occupied by the 8T cells (1.5x for MCU). Moreover, the trend for events affecting multiple bits was higher in 6T-cells. The cross-section obtained values show that the memories have enough sensitivity to be used as a radiation monitors in high energy physics experiments.