Sub-40mV Sigma-VTH IGZO nFETs in 300mm Fab

TL;DR

This paper reports the successful fabrication of sub-40mV sigma-VTH IGZO nFETs in a 300mm fab, highlighting optimized back-gate processing, material engineering, and a new IGZO phase for improved VTH_ON control.

Contribution

It introduces a scaled back gated flow with optimized design of experiments and a new IGZO phase, achieving ultra-low sigma-VTH in IGZO nFETs.

Findings

Demonstrated sub-40mV sigma-VTH in IGZO nFETs.

Optimized back-gate processing improves VTH_ON control.

Proposed dopant location model explains experimental results.

Abstract

Back and double gate IGZO nFETs have been demonstrated down to 120nm and 70nm respectively leveraging 300mm fab processing. While the passivation of oxygen vacancies in IGZO is challenging with an integration of front side gate, a scaled back gated flow has been optimized by multiplying design of experiments around contacts and material engineering. We then successfully demonstrated sub-40mV $\sigma$(VTH_ON) in scaled IGZO nFETs. Regarding the performance and the VTH_ON control, a new IGZO phase is also reported. A model of dopants location is proposed to better explain the experimental results reported in literature.