UVLLM: An Automated Universal RTL Verification Framework using LLMs

TL;DR

UVLLM leverages Large Language Models combined with UVM to automate and improve RTL verification, achieving high error fix rates and addressing limitations of existing methods.

Contribution

Introduces UVLLM, a novel framework integrating LLMs with UVM to enhance automation and error detection in RTL verification.

Findings

Syntax error fix rate of 86.99%

Functional error fix rate of 71.92%

Significant improvement in verification efficiency

Abstract

Verifying hardware designs in embedded systems is crucial but often labor-intensive and time-consuming. While existing solutions have improved automation, they frequently rely on unrealistic assumptions. To address these challenges, we introduce a novel framework, UVLLM, which combines Large Language Models (LLMs) with the Universal Verification Methodology (UVM) to relax these assumptions. UVLLM significantly enhances the automation of testing and repairing error-prone Register Transfer Level (RTL) codes, a critical aspect of verification development. Unlike existing methods, UVLLM ensures that all errors are triggered during verification, achieving a syntax error fix rate of 86.99% and a functional error fix rate of 71.92% on our proposed benchmark. These results demonstrate a substantial improvement in verification efficiency. Additionally, our study highlights the current limitations of LLM applications, particularly their reliance on extensive training data. We emphasize the transformative potential of LLMs in hardware design verification and suggest promising directions for future research in AI-driven hardware design methodologies. The Repo. of dataset and code: https://anonymous.4open.science/r/UVLLM/.