An Affordable Experimental Technique for SRAM Write Margin Characterization for Nanometer CMOS Technologies

TL;DR

This paper introduces a low-cost, non-intrusive method called Word Line Voltage Margin (WLVM) for accurately measuring SRAM write stability in nanometer CMOS technologies, addressing variability and reliability challenges.

Contribution

It proposes the WLVM metric for experimental SRAM stability assessment with minimal design changes, validated through measurements in 65 nm CMOS SRAM prototypes.

Findings

WLVM correlates well with existing writability metrics.

The method effectively characterizes write stability post-process.

Transistor width impacts WLVM measurements.

Abstract

Increased process variability and reliability issues present a major challenge for future SRAM trends. Non-intrusive and accurate SRAM stability measurement is crucial for estimating yield in large SRAM arrays. Conventional SRAM variability metrics require including test structures that cannot be used to investigate cell bit fails in functional SRAM arrays. This work proposes the Word Line Voltage Margin (WLVM), defined as the maximum allowed word-line voltage drop during write operations, as a metric for the experimental characterization of write stability of SRAM cells. Their experimental measurement can be attained with minimal design modifications, while achieving good correlation with existing writability metrics. To demonstrate its feasibility, the distribution of WLVM values has been measured in an SRAM prototype implemented in 65 nm CMOS technology. The dependence of the metric with the width of the transistors has been also analysed, demonstrating their utility in post-process write stability characterization.