Mera: Memory Reduction and Acceleration for Quantum Circuit Simulation via Redundancy Exploration

TL;DR

Mera introduces a multi-level optimization approach that reduces memory usage and accelerates quantum circuit simulation by exploiting redundancy, enabling simulation of more qubits and faster neural network computations.

Contribution

The paper presents novel compressed structures and optimization techniques for simulating large-scale quantum circuits more efficiently on classical computers.

Findings

Simulates up to 35 qubits, surpassing previous limits.

Achieves up to 6.9 times acceleration for quantum neural networks.

Reduces memory requirements significantly for dense and sparse quantum gates.

Abstract

With the development of quantum computing, quantum processor demonstrates the potential supremacy in specific applications, such as Grovers database search and popular quantum neural networks (QNNs). For better calibrating the quantum algorithms and machines, quantum circuit simulation on classical computers becomes crucial. However, as the number of quantum bits (qubits) increases, the memory requirement grows exponentially. In order to reduce memory usage and accelerate simulation, we propose a multi-level optimization, namely Mera, by exploring memory and computation redundancy. First, for a large number of sparse quantum gates, we propose two compressed structures for low-level full-state simulation. The corresponding gate operations are designed for practical implementations, which are relieved from the longtime compression and decompression. Second, for the dense Hadamard gate, which is definitely used to construct the superposition, we design a customized structure for significant memory saving as a regularity-oriented simulation. Meanwhile, an ondemand amplitude updating process is optimized for execution acceleration. Experiments show that our compressed structures increase the number of qubits from 17 to 35, and achieve up to 6.9 times acceleration for QNN.