Versatile Top-Down Patterning Technique for Perovskite On-Chip Integration

TL;DR

This paper presents a versatile top-down patterning method for perovskite films, enabling high-resolution, scalable on-chip integration crucial for optoelectronic applications, overcoming challenges posed by their ionic nature.

Contribution

The authors develop a novel photolithography and RIE-based patterning technique compatible with various perovskite compositions and morphologies, achieving micron-scale features with high reproducibility.

Findings

Achieved micron-sized patterning down to 1 μm.

Validated patterning quality with AFM, XRD, SEM, and optical spectroscopy.

Demonstrated scalable, high-throughput on-chip integration of perovskites.

Abstract

Metal-halide perovskites (MHPs) have exciting optoelectronic properties and are under investigation for various applications, such as photovoltaics, light-emitting diodes, and lasers. An essential step towards exploiting the full potential of this class of materials is their large-scale, on-chip integration with high-resolution, top-down patterning. The development of such patterning methods for perovskite films is challenging because of their intrinsic ionic nature and adverse reactions with the solvents used in standard lithography processes. Here, we introduce a versatile and precise method comprising photolithography and reactive ion etching (RIE) processes that can be tuned to accommodate different perovskite compositions and morphologies. Our method utilizes conventional photoresists at reduced temperatures to create micron-sized features down to 1 ${\mu}$m, providing high reproducibility from chip to chip. The patterning technique is validated through atomic force microscopy (AFM), X-ray diffraction (XRD), optical spectroscopy, and scanning electron microscopy (SEM). It enables the scalable and high-throughput on-chip monolithic integration of MHPs.