AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs

TL;DR

AssertLLM is an automated framework that leverages multi-LLMs to generate hardware verification assertions directly from complete design specifications, including natural language and waveform diagrams, improving accuracy and quality.

Contribution

This work introduces AssertLLM, a novel multi-LLM-based system that automatically converts full specification documents into verification assertions, addressing limitations of prior sentence-based methods.

Findings

AssertLLM produces more accurate assertions than GPT-4o and GPT-3.5.

The framework effectively processes both natural language and waveform diagrams.

Automates assertion generation from complete specifications, reducing human effort.

Abstract

Assertion-based verification (ABV) is a critical method to ensure logic designs comply with their architectural specifications. ABV requires assertions, which are generally converted from specifications through human interpretation by verification engineers. Existing methods for generating assertions from specification documents are limited to sentences extracted by engineers, discouraging their practical applications. In this work, we present AssertLLM, an automatic assertion generation framework that processes complete specification documents. AssertLLM can generate assertions from both natural language and waveform diagrams in specification files. It first converts unstructured specification sentences and waveforms into structured descriptions using natural language templates. Then, a customized Large Language Model (LLM) generates the final assertions based on these descriptions. Our evaluation demonstrates that AssertLLM can generate more accurate and higher-quality assertions compared to GPT-4o and GPT-3.5.