RISecure-PUF: Multipurpose PUF-Driven Security Extensions with Lookaside Buffer in RISC-V

TL;DR

RISecure-PUF enhances RISC-V security by integrating PUF-based key generation, a hash function for security, and a lookaside buffer for faster batch sampling, with minimal hardware overhead on FPGA.

Contribution

This work introduces RISecure-PUF, combining PUFs, hashing, and buffering to improve security and performance in RISC-V systems.

Findings

At least 2.72× speedup in batch sampling

Negligible hardware overhead

Maximum 10.7% performance reduction

Abstract

RISC-V's limited security features hinder its use in confidential computing and heterogeneous platforms. This paper introduces RISecure-PUF, a security extension utilizing existing Physical Unclonable Functions for key generation and secure protocol purposes. A one-way hash function is integrated to ensure provable security against modeling attacks, while a lookaside buffer accelerates batch sampling and minimizes reliance on error correction codes. Implemented on the Genesys 2 FPGA, RISecure-PUF improves at least $2.72\times$ in batch scenarios with negligible hardware overhead and a maximum performance reduction of $10.7\%$, enabled by reusing the hash function module in integrated environments such as cryptographic engines.