Veryl: A New Hardware Description Language as an Altarnative to SystemVerilog

TL;DR

Veryl is a new hardware description language based on SystemVerilog, designed to improve syntax, readability, and tooling support for logic design, facilitating easier integration and more efficient hardware development.

Contribution

It introduces a syntax-optimized HDL that enhances readability and tooling support while maintaining compatibility with SystemVerilog.

Findings

Ensures synthesizability with simplified constructs

Provides comprehensive development tools

Facilitates smooth SystemVerilog integration

Abstract

Veryl, a hardware description language based on SystemVerilog, offers optimized syntax tailored for logic design, ensuring synthesizability and simplifying common constructs. It prioritizes interoperability with SystemVerilog, allowing for smooth integration with existing projects while maintaining high readability. Additionally, Veryl includes a comprehensive set of development support tools, such as package managers and real-time checkers, to boost productivity and streamline the design process. These features empower designers to conduct high-quality hardware design efficiently.