MORE-Stress: Model Order Reduction based Efficient Numerical Algorithm for Thermal Stress Simulation of TSV Arrays in 2.5D/3D IC

TL;DR

This paper introduces MORE-Stress, a model order reduction algorithm that significantly accelerates thermal stress simulations of TSV arrays in 2.5D/3D ICs, reducing computational time and memory while maintaining high accuracy.

Contribution

The paper presents a novel numerical algorithm based on model order reduction for efficient thermal stress simulation of TSV arrays, outperforming existing methods in speed and memory usage.

Findings

Achieves 153-504x faster computation than ANSYS

Reduces memory usage by 39-115x

Maintains errors below 1% with fast convergence

Abstract

Thermomechanical stress induced by through-silicon vias (TSVs) plays an important role in the performance and reliability analysis of 2.5D/3D ICs. While the finite element method (FEM) adopted by commercial software can provide accurate simulation results, it is very time- and memory-consuming for large-scale analysis. Over the past decade, the linear superposition method has been utilized to perform fast thermal stress estimations of TSV arrays, but it suffers from a lack of accuracy. In this paper, we propose MORE-Stress, a novel strict numerical algorithm for efficient thermal stress simulation of TSV arrays based on model order reduction. Extensive experimental results demonstrate that our algorithm can realize a 153-504 times reduction in computational time and a 39-115 times reduction in memory usage compared with the commercial software ANSYS, with negligible errors less than 1%. Our algorithm is as efficient as the linear superposition method, with an order of magnitude smaller errors and fast convergence.