Advancing Cloud Computing Capabilities on gem5 by Implementing the RISC-V Hypervisor Extension

TL;DR

This paper implements and evaluates the RISC-V hypervisor extension within the gem5 simulator, enhancing virtualization capabilities and providing insights into performance and correctness for cloud computing applications.

Contribution

It introduces the architectural integration of the RISC-V H extension into gem5, detailing modifications and evaluating its impact on simulation accuracy and performance.

Findings

Successful implementation of RISC-V H extension in gem5

Performance evaluation shows acceptable overhead

Provides a foundation for future virtualization research

Abstract

This paper presents the implementation and evaluation of the H (hypervisor) extension for the RISC-V instruction set architecture (ISA) on top of the gem5 microarchitectural simulator. The RISC-V ISA, known for its simplicity and modularity, has seen widespread adoption in various computing domains. The H extension aims to enhance RISC-V's capabilities for cloud computing and virtualization. In this paper, we present the architectural integration of the H extension into gem5, an open-source, modular platform for computer system architecture research. We detail the modifications required in gem5's CPU models and virtualization support to accommodate the H extension. We also present evaluation results regarding the performance impact and functional correctness of the extension's implementation on gem5. This study not only provides a pathway for further research and development of RISC-V extensions but also contributes valuable insights into the optimization of the gem5 simulator for advanced architectural features.