HW/SW Implementation of MiRitH on Embedded Platforms

TL;DR

This paper explores the implementation of the MiRitH multi-party computation algorithm on embedded platforms, demonstrating its viability through hardware/software co-design and resource optimization on FPGA devices.

Contribution

It presents the first design space exploration of MiRitH on embedded devices, including a HW/SW library and analysis of optimal solutions under resource constraints.

Findings

MiRitH is feasible for embedded devices in terms of runtime.

The HW/SW library enables efficient FPGA resource utilization.

Optimal solutions depend on specific runtime and resource constraints.

Abstract

Multi-Party Computation in the Head (MPCitH) algorithms are appealing candidates in the additional US NIST standardization rounds for Post-Quantum Cryptography (PQC) with respect to key sizes and mathematical hardness assumptions. However, their complexity presents a significant challenge for platforms with limited computational capabilities. To address this issue, we present, to the best of our knowledge, the first design space exploration of MiRitH, a promising MPCitH algorithm, for embedded devices. We develop a library of mixed HW/SW blocks on the Xilinx ZYNQ 7000, and, based on this library, we explore optimal solutions under runtime or FPGA resource constraints for a given public key infrastructure. Our results show that MiRitH is a viable algorithm for embedded devices in terms of runtime and FPGA resource requirements.