Automatically Improving LLM-based Verilog Generation using EDA Tool Feedback
Jason Blocklove, Shailja Thakur, Benjamin Tan, Hammond Pearce,, Siddharth Garg, Ramesh Karri

TL;DR
This paper presents AutoChip, a framework that uses EDA tool feedback to iteratively improve LLM-generated Verilog code, significantly enhancing success rates and reducing costs compared to zero-shot approaches.
Contribution
The work introduces AutoChip, an open-source framework that leverages EDA feedback with conversational LLMs to improve Verilog generation, demonstrating effectiveness with commercial models.
Findings
EDA feedback improves success rates, especially with GPT-4o.
Best case shows 5.8% more successful designs.
Mixing models reduces costs by 41.9%.
Abstract
Traditionally, digital hardware designs are written in the Verilog hardware description language (HDL) and debugged manually by engineers. This can be time-consuming and error-prone for complex designs. Large Language Models (LLMs) are emerging as a potential tool to help generate fully functioning HDL code, but most works have focused on generation in the single-shot capacity: i.e., run and evaluate, a process that does not leverage debugging and, as such, does not adequately reflect a realistic development process. In this work, we evaluate the ability of LLMs to leverage feedback from electronic design automation (EDA) tools to fix mistakes in their own generated Verilog. To accomplish this, we present an open-source, highly customizable framework, AutoChip, which combines conversational LLMs with the output from Verilog compilers and simulations to iteratively generate and repair…
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Taxonomy
TopicsSoftware Reliability and Analysis Research · Business Process Modeling and Analysis · Software Engineering Research
