An Efficient Multicast Addressing Encoding Scheme for Multi-Core Neuromorphic Processors

TL;DR

This paper introduces a hierarchical multicast addressing scheme for multi-core neuromorphic processors that significantly reduces area and energy costs, enhancing inter-core communication efficiency in event-based applications.

Contribution

The paper presents a novel hierarchical bit string encoding scheme that expands addressing capacity and improves energy efficiency for neuromorphic processors.

Findings

Reduces area cost by approximately 29%.

Decreases energy consumption by about 50%.

Enhances inter-core communication efficiency.

Abstract

Multi-core neuromorphic processors are becoming increasingly significant due to their energy-efficient local computing and scalable modular architecture, particularly for event-based processing applications. However, minimizing the cost of inter-core communication, which accounts for the majority of energy usage, remains a challenging issue. Beyond optimizing circuit design at lower abstraction levels, an efficient multicast addressing scheme is crucial. We propose a hierarchical bit string encoding scheme that largely expands the addressing capability of state-of-the-art symbol-based schemes for the same number of routing bits. When put at work with a real neuromorphic task, this hierarchical bit string encoding achieves a reduction in area cost by approximately 29% and decreases energy consumption by about 50%.