Timing-driven Approximate Logic Synthesis Based on Double-chase Grey Wolf Optimizer

TL;DR

This paper introduces a timing-driven approximate logic synthesis method using a double-chase grey wolf optimizer, achieving better critical path reduction and area optimization under error constraints for 28nm circuits.

Contribution

It proposes a novel optimization framework combining double-chase grey wolf optimizer with local approximate changes for improved timing and area trade-offs.

Findings

Achieves greater critical path delay reduction compared to state-of-the-art methods.

Effectively balances timing improvement and area reduction under error constraints.

Demonstrates superior performance on open-source circuits in 28nm technology.

Abstract

With the shrinking technology nodes, timing optimization becomes increasingly challenging. Approximate logic synthesis (ALS) can perform local approximate changes (LACs) on circuits to optimize timing with the cost of slight inaccuracy. However, existing ALS methods that focus solely on critical path depth reduction (depth-driven methods) or area minimization (area-driven methods) are inefficient in achieving optimal timing improvement. %based on double-chase grey wolf optimizer (DCGWO). where we employ a double-chase grey wolf optimizer to explore and apply LACs, simultaneously bringing excellent critical path shortening and area reduction under error constraints. According to experiments on open-source circuits with TSMC 28nm technology, compared to the SOTA method, our framework can generate approximate circuits with greater critical path delay reduction under different error and area constraints.