Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)

TL;DR

This paper introduces an automation tool for optimizing energy and latency in application-specific resonant SRAM compute-in-memory architectures, enabling rapid evaluation of diverse design strategies and significantly reducing energy consumption.

Contribution

The paper presents a novel automation framework for evaluating and optimizing SRAM-based compute-in-memory designs, facilitating comparison across multiple topologies and strategies for energy-efficient implementations.

Findings

Reduced 80.9% energy consumption on average across benchmarks.

Compared over 6900 design strategies for rCiM architectures.

Demonstrated effectiveness of six-topology implementation in energy savings.

Abstract

While general-purpose computing follows Von Neumann's architecture, the data movement between memory and processor elements dictates the processor's performance. The evolving compute-in-memory (CiM) paradigm tackles this issue by facilitating simultaneous processing and storage within static random-access memory (SRAM) elements. Numerous design decisions taken at different levels of hierarchy affect the figure of merits (FoMs) of SRAM, such as power, performance, area, and yield. The absence of a rapid assessment mechanism for the impact of changes at different hierarchy levels on global FoMs poses a challenge to accurately evaluating innovative SRAM designs. This paper presents an automation tool designed to optimize the energy and latency of SRAM designs incorporating diverse implementation strategies for executing logic operations within the SRAM. The tool structure allows easy comparison across different array topologies and various design strategies to result in energy-efficient implementations. Our study involves a comprehensive comparison of over 6900+ distinct design implementation strategies for EPFL combinational benchmark circuits on the energy-recycling resonant compute-in-memory (rCiM) architecture designed using TSMC 28 nm technology. When provided with a combinational circuit, the tool aims to generate an energy-efficient implementation strategy tailored to the specified input memory and latency constraints. The tool reduces 80.9% of energy consumption on average across all benchmarks while using the six-topology implementation compared to baseline implementation of single-macro topology by considering the parallel processing capability of rCiM cache size ranging from 4KB to 192KB.