AMARETTO: Enabling Efficient Quantum Algorithm Emulation on Low-Tier FPGAs

TL;DR

AMARETTO is a novel FPGA-based emulation platform that enables efficient and scalable simulation of quantum algorithms, supporting larger qubit systems on low-tier FPGAs, thus facilitating quantum algorithm validation.

Contribution

This work introduces AMARETTO, a new FPGA-based quantum emulator with a specialized compiler, capable of emulating larger qubit systems on affordable hardware, improving validation efficiency.

Findings

Successfully emulated 16 qubits on low-tier FPGA

Achieved performance comparable to higher-end emulators

Validated against Qiskit simulators

Abstract

Researchers and industries are increasingly drawn to quantum computing for its computational potential. However, validating new quantum algorithms is challenging due to the limitations of current quantum devices. Software simulators are time and memory-consuming, making hardware emulators an attractive alternative. This article introduces AMARETTO (quAntuM ARchitecture EmulaTion TechnOlogy), designed for quantum computing emulation on low-tier Field-Programmable gate arrays (FPGAs), supporting Clifford+T and rotational gate sets. It simplifies and accelerates the verification of quantum algorithms using a Reduced-Instruction-Set-Computer (RISC)-like structure and efficient handling of sparse quantum gates. A dedicated compiler translates OpenQASM 2.0 into RISC-like instructions. AMARETTO is validated against the Qiskit simulators. Our results show successful emulation of sixteen qubits on a AMD Kria KV260 SoM. This approach rivals other works in emulated qubit capacity on a smaller, more affordable FPGA