Reducing ADC Front-end Costs During Training of On-sensor Printed Multilayer Perceptrons

TL;DR

This paper proposes a method to optimize ADC design for printed multilayer perceptrons, significantly reducing area and energy costs while maintaining high classification accuracy, enabling more efficient on-sensor printed electronics.

Contribution

It introduces a training-integrated ADC optimization technique that minimizes ADC complexity by reducing levels, leading to substantial area savings without accuracy loss.

Findings

11.2x reduction in ADC area

Less than 5% accuracy drop

Effective for various MLP architectures

Abstract

Printed electronics technology offers a cost-effectiveand fully-customizable solution to computational needs beyondthe capabilities of traditional silicon technologies, offering ad-vantages such as on-demand manufacturing and conformal, low-cost hardware. However, the low-resolution fabrication of printedelectronics, which results in large feature sizes, poses a challengefor integrating complex designs like those of machine learn-ing (ML) classification systems. Current literature optimizes onlythe Multilayer Perceptron (MLP) circuit within the classificationsystem, while the cost of analog-to-digital converters (ADCs)is overlooked. Printed applications frequently require on-sensorprocessing, yet while the digital classifier has been extensivelyoptimized, the analog-to-digital interfacing, specifically the ADCs,dominates the total area and energy consumption. In this work,we target digital printed MLP classifiers and we propose thedesign of customized ADCs per MLP's input which involvesminimizing the distinct represented numbers for each input,simplifying thus the ADC's circuitry. Incorporating this ADCoptimization in the MLP training, enables eliminating ADC levelsand the respective comparators, while still maintaining highclassification accuracy. Our approach achieves 11.2x lower ADCarea for less than 5% accuracy drop across varying MLPs.