System-Level Analysis for mm-Wave Full-Duplex Transceivers

TL;DR

This paper provides a detailed system-level analysis of mm-Wave full-duplex transceivers, focusing on optimizing self-interference cancellation and component specifications to ensure reliable high-data-rate communication.

Contribution

It introduces a comprehensive methodology for determining noise and linearity requirements for each transceiver block in mm-Wave full-duplex systems, validated through simulation.

Findings

Optimized noise and linearity specifications for each transceiver component.

Validated the analysis with MATLAB Simulink simulations.

Established feasible SIC requirements for CMOS implementation.

Abstract

This paper conducts a comprehensive system-level analysis of mm-Wave full-duplex transceivers, focusing on a receiver employing a four-stage self-interference cancellation (SIC) process. The analysis aims to optimize the noise and linearity performance requirements of each transceiver block, ensuring that the self-interference (SI) signal does not compromise the receiver's error vector magnitude (EVM) for an OFDM 64-QAM signal. Additionally, the necessary SIC for each stage is calculated to establish feasible noise and linearity specifications for a CMOS-based implementation. The resulting specifications are subsequently validated within a MATLAB Simulink environment, confirming the accuracy of the computed requirements for each block.