RPCAcc: A High-Performance and Reconfigurable PCIe-attached RPC Accelerator
Jie Zhang, Hongjing Huang, Xuzheng Xu, Xiang Li, Jieru Zhao, Ming Liu,, Zeke Wang

TL;DR
RPCAcc is a reconfigurable PCIe-attached hardware accelerator for RPC that significantly reduces serialization overhead and improves throughput in cloud data center workloads.
Contribution
It introduces a novel software-hardware co-designed RPC accelerator connected via PCIe, with techniques to optimize data serialization and schema reconfiguration.
Findings
3.2X lower serialization time compared to baseline
up to 2.6X throughput improvement in cloud workloads
effective batching and schema reconfiguration techniques
Abstract
The emerging microservice/serverless-based cloud programming paradigm and the rising networking speeds leave the RPC stack as the predominant data center tax. Domain-specific hardware acceleration holds the potential to disentangle the overhead and save host CPU cycles. However, state-of-the-art RPC accelerators integrate RPC logic into the CPU or use specialized low-latency interconnects, hardly adopted in commodity servers. To this end, we design and implement RPCAcc, a software-hardware co-designed RPC on-NIC accelerator that enables reconfigurable RPC kernel offloading. RPCAcc connects to the server through the most widely used PCIe interconnect. To grapple with the ramifications of PCIe-induced challenges, RPCAcc introduces three techniques:(a) a target-aware deserializer that effectively batches cross-PCIe writes on the accelerator's on-chip memory using compacted hardware…
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Taxonomy
TopicsCCD and CMOS Imaging Sensors · Particle Detector Development and Performance · Embedded Systems Design Techniques
