A Simple Packing Algorithm for Optimized Mapping of Artificial Neural Networks onto Non-Volatile Memory Cross-Bar Arrays

TL;DR

This paper presents a simplified algorithm for mapping neural network layers onto crossbar arrays in neuromorphic chips, revealing that optimal performance depends on array capacity and peripheral circuit scaling, not just minimizing tile count.

Contribution

The paper introduces a new simplified mapping algorithm for neural networks on crossbar arrays, highlighting the importance of array capacity and peripheral circuit scaling over traditional minimization strategies.

Findings

Optimal mapping involves a trade-off between tile array capacity and peripheral circuit scaling.

Square arrays are not always optimal for neural network mapping.

Performance optimization may increase total tile area.

Abstract

Neuromorphic computing with crossbar arrays has emerged as a promising alternative to improve computing efficiency for machine learning. Previous work has focused on implementing crossbar arrays to perform basic mathematical operations. However, in this paper, we explore the impact of mapping the layers of an artificial neural network onto physical cross-bar arrays arranged in tiles across a chip. We have developed a simplified mapping algorithm to determine the number of physical tiles, with fixed optimal array dimensions, and to estimate the minimum area occupied by these tiles for a given design objective. This simplified algorithm is compared with conventional binary linear optimization, which solves the equivalent bin-packing problem. We have found that the optimum solution is not necessarily related to the minimum number of tiles; rather, it is shown to be an interaction between tile array capacity and the scaling properties of its peripheral circuits. Additionally, we have discovered that square arrays are not always the best choice for optimal mapping, and that performance optimization comes at the cost of total tile area