Increasing the scalability of graph convolution for FPGA-implemented event-based vision

TL;DR

This paper presents a hardware-optimized approach for graph convolution in FPGA-based event camera processing, significantly enhancing scalability and resource efficiency for dynamic vision applications.

Contribution

It introduces a two-step convolution method that reduces LUT usage by up to 94%, enabling more scalable GCNN deployment on FPGA hardware.

Findings

Reduces LUT usage by up to 94%

Enables deployment of deeper and larger GCNN models

Improves scalability for dynamic event-based vision scenarios

Abstract

Event cameras are becoming increasingly popular as an alternative to traditional frame-based vision sensors, especially in mobile robotics. Taking full advantage of their high temporal resolution, high dynamic range, low power consumption and sparsity of event data, which only reflects changes in the observed scene, requires both an efficient algorithm and a specialised hardware platform. A recent trend involves using Graph Convolutional Neural Networks (GCNNs) implemented on a heterogeneous SoC FPGA. In this paper we focus on optimising hardware modules for graph convolution to allow flexible selection of the FPGA resource (BlockRAM, DSP and LUT) for their implementation. We propose a ''two-step convolution'' approach that utilises additional BRAM buffers in order to reduce up to 94% of LUT usage for multiplications. This method significantly improves the scalability of GCNNs, enabling the deployment of models with more layers, larger graphs sizes and their application for more dynamic scenarios.