Reusable Verification Components for High-Energy Physics readout ASICs

TL;DR

This paper introduces reusable verification components designed for front-end ASICs in High-Energy Physics, streamlining common verification tasks and improving efficiency across multiple projects.

Contribution

It presents a set of modular, reusable verification components that address common tasks in HEP ASIC verification, developed within the CHIPS initiative.

Findings

Successfully used in multiple HEP ASIC verifications

Improved verification efficiency and consistency

Reusable components for clock, reset, configuration, and fault injection

Abstract

Verification is a critical aspect of designing front-end (FE) readout ASICs for High-Energy Physics (HEP) experiments. These ASICs share several similar functional features, resulting in similar verification objectives, which can be addressed using comparable verification strategies. This contribution presents a set of re-usable verification components for addressing common verification tasks, such as clock generation, reset handling, configuration, as well as hit and fault injections. The components were developed as part of the CHIPS initiative and they have been successfully used in the verification of multiple HEP ASICs.