Quantum Error Mitigation via Linear-Depth Verifier Circuits

TL;DR

This paper introduces verifier circuit architectures for quantum error mitigation that are efficient and high-fidelity, enabling calibration of quantum sub-circuits on near-term devices despite noise challenges.

Contribution

It proposes a method to construct verifier circuits for low-MPO quantum circuits and demonstrates their application to important quantum gates and the QFT.

Findings

Verifier circuits can be shallower than the original circuits for certain cases.

The approach is useful for calibrating quantum sub-circuits against coherent noise.

Cannot correct incoherent noise in current devices.

Abstract

Implementing many important sub-circuits on near-term quantum devices remains a challenge due to the high levels of noise and the prohibitive depth on standard nearest-neighbour topologies. Overcoming these barriers will likely require quantum error mitigation (QEM) strategies. This work introduces the notion of efficient, high-fidelity verifier circuit architectures that we propose for use in such a QEM scheme. We provide a method for constructing verifier circuits for any quantum circuit that is accurately represented by a low-dimensional matrix product operator (MPO). We demonstrate our method by constructing explicit verifier circuits for multi-controlled single unitary gates as well as the quantum Fourier transform (QFT). By transpiling the circuits to a 2D array of qubits, we estimate the crossover point where the verifier circuit is shallower than the circuit itself, and hence useful for QEM. We propose a method of in situ QEM using the verifier circuit architecture. We conclude that our approach may be useful for calibrating quantum sub-circuits to counter coherent noise but cannot correct for the incoherent noise present in current devices.