ZipCache: A DRAM/SSD Cache with Built-in Transparent Compression

TL;DR

ZipCache is a hybrid DRAM-SSD key-value cache system that integrates transparent compression, significantly improving throughput, latency, and reducing write amplification through redesigned data management and hardware collaboration.

Contribution

The paper introduces ZipCache, a novel cache architecture that systematically incorporates compression with redesigned indexing and SSD hardware support for improved performance.

Findings

Achieves up to 72.4% higher throughput

Reduces latency by 42.4%

Decreases write amplification by 26.2 times

Abstract

As a core component in modern data centers, key-value cache provides high-throughput and low-latency services for high-speed data processing. The effectiveness of a key-value cache relies on its ability of accommodating the needed data. However, expanding the cache capacity is often more difficult than commonly expected because of many practical constraints, such as server costs, cooling issues, rack space, and even human resource expenses. A potential solution is compression, which virtually extends the cache capacity by condensing data in cache. In practice, this seemingly simple idea has not gained much traction in key-value cache system design, due to several critical issues: the compression-unfriendly index structure, severe read/write amplification, wasteful decompression operations, and heavy computing cost. This paper presents a hybrid DRAM-SSD cache design to realize a systematic integration of data compression in key-value cache. By treating compression as an essential component, we have redesigned the indexing structure, data management, and leveraged the emerging computational SSD hardware for collaborative optimizations. We have developed a prototype, called ZipCache. Our experimental results show that ZipCache can achieve up to 72.4% higher throughput and 42.4% lower latency, while reducing the write amplification by up to 26.2 times.