Optimized Cryo-CMOS Technology with VTH<0.2V and Ion>1.2mA/um for High-Peformance Computing

TL;DR

This paper presents a co-optimized 28-nm cryo-CMOS technology with low VTH and high Ion, enabling high-performance computing at cryogenic temperatures with significant speed and power efficiency improvements.

Contribution

The study introduces a novel DTCO scheme for cryo-CMOS, achieving VTH<0.2V, SS<30 mV/dec, and Ion>1.2mA/um at 77K, with enhanced oscillator frequency and reduced power consumption.

Findings

20% increase in ring oscillator frequency

37% reduction in power consumption at 77K

VTH<0.2V and Ion>1.2mA/um at cryogenic temperatures

Abstract

We report the design-technology co-optimization (DTCO) scheme to develop a 28-nm cryogenic CMOS (Cryo-CMOS) technology for high-performance computing (HPC). The precise adjustment of halo implants manages to compensate the threshold voltage (VTH) shift at low temperatures. The optimized NMOS and PMOS transistors, featured by VTH<0.2V, sub-threshold swing (SS)<30 mV/dec, and on-state current (Ion)>1.2mA/um at 77K, warrant a reliable sub-0.6V operation. Moreover, the enhanced driving strength of Cryo-CMOS inherited from a higher transconductance leads to marked improvements in elevating the ring oscillator frequency by 20%, while reducing the power consumption of the compute-intensive cryogenic IC system by 37% at 77K.