Technical challenges designing a prototype common readout board for LHCb future upgrades
Julien Jiro Langou\"et (on behalf of the PCIe400 development, collaboration)
TL;DR
This paper discusses the design challenges and solutions for a prototype readout board for LHCb's future upgrades, focusing on high throughput, precise clock distribution, and thermal management.
Contribution
It presents the development of a high-performance readout board prototype with innovative solutions for thermal, power, and signal integrity challenges.
Findings
Achieved 400Gbps bandwidth with FPGA-based design
Improved stripline simulation methods reduced processing time
Addressed thermal dissipation and power consumption exceeding 220 watts
Abstract
The LHCb Upgrade I introduced a triggerless data acquisition system, crucial for readout across sub-detectors. Upgrade II aims for fivefold throughput enhancement and requires precise clock distribution. The PCIe400 development significantly boosts performance with 400Gbps bandwidth and advanced FPGA capabilities. Key design considerations included thermal dissipation, power distribution, and signal integrity, addressing power consumption exceeding 220 watts. Additionally, advancements in striplines were achieved through improved simulation methods, reducing processing times while optimizing geometry for performance.
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