Energy-Aware FPGA Implementation of Spiking Neural Network with LIF Neurons

TL;DR

This paper introduces an energy-efficient FPGA implementation of a spiking neural network using LIF neurons, optimized for TinyML vision applications, demonstrating significant power savings over existing methods.

Contribution

It presents a novel FPGA-based SNN architecture with a hardware-friendly LIF neuron design tailored for TinyML, and evaluates its energy efficiency on a collision avoidance task.

Findings

Achieved 86% energy efficiency improvement over baseline methods

Implemented on Xilinx Artix-7 FPGA for real-time vision tasks

Demonstrated suitability for IoT applications with low power constraints

Abstract

Tiny Machine Learning (TinyML) has become a growing field in on-device processing for Internet of Things (IoT) applications, capitalizing on AI algorithms that are optimized for their low complexity and energy efficiency. These algorithms are designed to minimize power and memory footprints, making them ideal for the constraints of IoT devices. Within this domain, Spiking Neural Networks (SNNs) stand out as a cutting-edge solution for TinyML, owning to their event-driven processing paradigm which offers an efficient method of handling dataflow. This paper presents a novel SNN architecture based on the 1st Order Leaky Integrate-and-Fire (LIF) neuron model to efficiently deploy vision-based ML algorithms on TinyML systems. A hardware-friendly LIF design is also proposed, and implemented on a Xilinx Artix-7 FPGA. To evaluate the proposed model, a collision avoidance dataset is considered as a case study. The proposed SNN model is compared to the state-of-the-art works and Binarized Convolutional Neural Network (BCNN) as a baseline. The results show the proposed approach is 86% more energy efficient than the baseline.