An Integer-N Frequency Synthesizer for Flexible On-Chip Clock Generation

TL;DR

This paper presents a low-power, flexible integer-N frequency synthesizer in 65 nm CMOS that generates two independent, low-jitter clocks from 30 MHz to 3 GHz, suitable for on-chip applications.

Contribution

It introduces a novel low-power integer-N synthesizer with dual outputs and wide frequency range, optimized for on-chip clock generation in 65 nm CMOS technology.

Findings

Operates from 30 MHz to 3 GHz with low jitter

Consumes only 4.0 mW power

Successfully demonstrated in experimental tests

Abstract

A low-power integer-N frequency synthesizer for flexible on-chip clock generation has been designed in 65 nm CMOS technology. The circuit can be programmed to generate two independent low-jitter clocks between 30 MHz and 3 GHz that are locked a 10-50 MHz reference input. The design uses a phase-locked loop (PLL) with a dual-tuned LC voltage-controlled oscillator (VCO), programmable feedback divider, and dual output dividers. The total power consumption from 1.2 V and 0.8 V supplies is 4.0 mW. Experimental results confirm the functionality of the proposed synthesizer over a wide range of output frequencies.