BF-IMNA: A Bit Fluid In-Memory Neural Architecture for Neural Network Acceleration
Mariam Rakka, Rachid Karami, Ahmed M. Eltawil, Mohammed E. Fouda, and, Fadi Kurdahi

TL;DR
BF-IMNA is a novel in-memory neural network accelerator supporting flexible mixed-precision computation without reconfiguration, achieving high energy efficiency and throughput for CNN inference on various hardware technologies.
Contribution
This paper introduces BF-IMNA, a bit fluid IMC accelerator capable of dynamic mixed-precision processing with no hardware reconfiguration overhead.
Findings
Achieves end-to-end ImageNet inference on AlexNet, VGG16, ResNet50.
Demonstrates trade-offs between accuracy and energy-delay with mixed-precision configurations.
Outperforms current accelerators in energy efficiency and throughput.
Abstract
Mixed-precision quantization works Neural Networks (NNs) are gaining traction for their efficient realization on the hardware leading to higher throughput and lower energy. In-Memory Computing (IMC) accelerator architectures are offered as alternatives to traditional architectures relying on a data-centric computational paradigm, diminishing the memory wall problem, and scoring high throughput and energy efficiency. These accelerators can support static fixed-precision but are not flexible to support mixed-precision NNs. In this paper, we present BF-IMNA, a bit fluid IMC accelerator for end-to-end Convolutional NN (CNN) inference that is capable of static and dynamic mixed-precision without any hardware reconfiguration overhead at run-time. At the heart of BF-IMNA are Associative Processors (APs), which are bit-serial word-parallel Single Instruction, Multiple Data (SIMD)-like engines.…
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Taxonomy
TopicsNeural Networks and Applications
