From Flip FET to Flip 3D Integration (F3D): Maximizing the Scaling Potential of Wafer Both Sides Beyond Conventional 3D Integration

TL;DR

This paper introduces Flip 3D integration (F3D), a novel 3D stacking technology that enhances scaling, routing flexibility, and performance of wafer-level devices through innovative stacking and interconnect techniques.

Contribution

The paper presents a new 3D integration method, F3D, combining multiple stacking and interconnect strategies, and introduces Multi-Flipping processes to improve thermal management and device performance.

Findings

6.8% area reduction due to dual-sided routing

5.9% EDP improvement from routing flexibility

up to 3.2% EDP and 2.3% frequency enhancement with BEOL optimization

Abstract

In this work, we proposed a new 3D integration technology: the Flip 3D integration (F3D), consisting of the 3D transistor stacking, the 3D dual-sided interconnects, the 3D die-to-die stacking and the dual-sided Monolithic 3D (M3D). Based on a 32-bit FFET RISCV core, besides the scaling benefits of the Flip FET (FFET), the dual-sided signal routing shows even more routing flexibility with 6.8% area reduction and 5.9% EDP improvement. Novel concepts of Multi-Flipping processes (Double Flips and Triple Flips) were proposed to relax the thermal budget constraints in the F3D and thus support the dual-sided M3D in the F3D. The core's EDP and frequency are improved by up to 3.2% and 2.3% respectively, after BEOL optimizations based on the Triple Flips compared with unoptimized ones.