An Event-Based Digital Compute-In-Memory Accelerator with Flexible Operand Resolution and Layer-Wise Weight/Output Stationarity

TL;DR

This paper introduces a flexible digital compute-in-memory accelerator for spiking neural networks that enhances energy efficiency and resolution configurability, enabling practical edge vision applications with high accuracy.

Contribution

It presents a novel digital CIM macro supporting arbitrary operand resolution and shape, with a hybrid dataflow for improved operand reuse and energy savings.

Findings

2× energy efficiency improvement over prior digital CIM-SNNs

Supports bitwise resolution reconfiguration

Achieves 95.8% accuracy on IBM DVS gesture dataset

Abstract

Compute-in-memory (CIM) accelerators for spiking neural networks (SNNs) are promising solutions to enable $\mu$s-level inference latency and ultra-low energy in edge vision applications. Yet, their current lack of flexibility at both the circuit and system levels prevents their deployment in a wide range of real-life scenarios. In this work, we propose a novel digital CIM macro that supports arbitrary operand resolution and shape, with a unified CIM storage for weights and membrane potentials. These circuit-level techniques enable a hybrid weight- and output-stationary dataflow at the system level to maximize operand reuse, thereby minimizing costly on- and off-chip data movements during the SNN execution. Measurement results of a fabricated FlexSpIM prototype in 40-nm CMOS demonstrate a 2$\times$ increase in bit-normalized energy efficiency compared to prior fixed-precision digital CIM-SNNs, while providing resolution reconfiguration with bitwise granularity. Our approach can save up to 90% energy in large-scale systems, while reaching a state-of-the-art classification accuracy of 95.8% on the IBM DVS gesture dataset.