Architectural Solutions for High-Speed Data Processing Demands of CERN LHC Detectors with FPGA and High-Level Synthesis

TL;DR

This paper explores FPGA-based implementation of a complex tau lepton triggering algorithm for CERN's upgraded LHC detectors, utilizing High-Level Synthesis to meet high data rate processing demands.

Contribution

It introduces a novel FPGA implementation approach for a complex trigger algorithm using HLS, including architectural optimizations for high-speed data processing.

Findings

Successful FPGA implementation of tau lepton trigger algorithm

Evaluation of various architectural solutions and optimizations

Demonstrated feasibility for real-time data processing at CERN

Abstract

The planned high-luminosity upgrade of the Large Hadron Collider (LHC) at CERN will bring much higher data rates that are far above the capabilities of currently installed software-based data processing systems. Therefore, new methods must be used to facilitate on-the-fly extraction of scientifically significant information from the immense flow of data produced by LHC particle detectors. This paper focuses on implementation of a tau lepton triggering algorithm in FPGA. Due to the algorithm's complexity and strict technical requirements, its implementation in FPGA fabric becomes a particularly challenging task. The paper presents a study of algorithm development with the help of High-Level Synthesis (HLS) technique that can generate hardware description from C++ code. Various architectural solutions and optimizations that were tried out during the design architecture exploration process are also discussed in the paper.