A Modulo Sampling Hardware Prototype and Reconstruction Algorithm Evaluation

TL;DR

This paper presents a hardware prototype and algorithms for modulo sampling that extend ADC dynamic range, demonstrating successful signal recovery with signals exceeding the ADC's range by tenfold.

Contribution

It introduces a novel modulo sampling hardware and a new USLSE algorithm for signal reconstruction, addressing implementation challenges and improving ADC performance.

Findings

USLSE recovers 2.5 kHz signals with 10x ADC range

Linear prediction recovers 3.5 kHz signals with 10x ADC range

Hardware prototype validates the modulo sampling approach

Abstract

Analog-to-digital converters (ADCs) play a vital important role in any devices via manipulating analog signals in a digital manner. Given that the amplitude of the signal exceeds the dynamic range of the ADCs, clipping occurs and the quality of the digitized signal degrades significantly. In this paper, we design a joint modulo sampling hardware and processing prototype which improves the ADCs' dynamic range by folding the signal before sampling. Both the detailed design of the hardware and the recovery results of various state-of-the-art processing algorithms including our proposed unlimited sampling line spectral estimation (USLSE) algorithm are presented. Additionally, key issues that arise during implementation are also addressed. It is demonstrated that the USLSE algorithm successfully recovers the original signal with a frequency of 2.5 kHz and an amplitude 10 times the ADC's dynamic range, and the linear prediction (LP) algorithm successfully recovers the original signal with a frequency of 3.5 kHz and an amplitude 10 times the ADC's dynamic range.