Statistical Analysis of Spurious Dot Formation in SiMOS Single Electron Transistors

TL;DR

This study statistically analyzes the spatial distribution of spurious dots in SiMOS single-electron transistors, revealing strain and gate bias as key factors influencing their formation, which can guide device optimization.

Contribution

It identifies the combined effects of strain and gate bias as primary causes of spurious dots, providing insights for reducing their density in device fabrication.

Findings

Most spurious dots are caused by strain and gate bias effects.

Strain remains significant despite similar thermal expansion coefficients.

Optimizing oxide thickness can reduce spurious dot density.

Abstract

The spatial distribution of spurious dots in SiMOS single-electron transistors (SETs), fabricated on an industrial 300 mm process line, has been statistically analyzed. To have a deeper understanding of the origin of these spurious dots, we analyzed SETs with three different oxide thicknesses: 8 nm, 12 nm and 20 nm. By combining spurious dot triangulation cryo-measurement with simulations of strain, gate bias, and location of the electron wave function, we demonstrate that most spurious dots are formed through the combined effects of strain and gate bias, leading to variations in the conduction band energy. Despite the similar thermal expansion coefficients of polycrystalline silicon gates and single-crystalline silicon substrates, strain remains a crucial factor in spurious dots formation. This learning can be use to optimize the device design and the oxide thickness, to reduce the density of spurious dot while keeping quantum dot tunability.