Automatic Extraction and Compensation of P-Bit Device Variations in Large Array Utilizing Boltzmann Machine Training
Bolin Zhang, Yu Liu, Tianqi Gao, Jialiang Yin, Zhenyu Guan, Deming, Zhang, Lang Zeng

TL;DR
This paper introduces a novel method combining a behavioral model, Boltzmann machine learning, and an Ising Hamiltonian to automatically extract and compensate device variations in large P-Bit arrays, enhancing the practicality of Ising computation.
Contribution
It presents a scalable automatic variation extraction algorithm and a weight compensation method for large P-Bit arrays, enabling accurate Ising computations despite device variations.
Findings
Successfully extracted device variations in large P-Bit arrays.
Demonstrated accurate solutions to TSP and integer factorization problems.
Showed the method's transferability and scalability in practical applications.
Abstract
Probabilistic Bit (P-Bit) device serves as the core hardware for implementing Ising computation. However, the severe intrinsic variations of stochastic P-Bit devices hinder the large-scale expansion of the P-Bit array, significantly limiting the practical usage of Ising computation. In this work, a behavioral model which attributes P-Bit variations to two parameters {\alpha} and {\Delta}V is proposed. Then the weight compensation method is introduced, which can mitigate {\alpha} and {\Delta}V of P-Bits device variations by rederiving the weight matrix, enabling them to compute as ideal identical PBits without the need for weights retraining. Accurately extracting the {\alpha} and {\Delta}V simultaneously from a large P-Bit array which is prerequisite for the weight compensation method is a crucial and challenging task. To solve this obstacle, we present the novel automatic variation…
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Taxonomy
TopicsIntegrated Circuits and Semiconductor Failure Analysis · VLSI and Analog Circuit Testing · Radio Frequency Integrated Circuit Design
