Towards Efficient IMC Accelerator Design Through Joint Hardware-Workload Co-optimization

TL;DR

This paper introduces a joint hardware-workload optimization framework for in-memory computing accelerators, significantly improving efficiency and flexibility across diverse workloads by optimizing architecture parameters collectively.

Contribution

It presents a novel joint optimization approach that outperforms separate workload-specific designs, enabling more efficient generalized IMC hardware.

Findings

Achieves up to 69% better energy-latency-area scores for various CNNs.

Quantifies performance trade-offs of generalized versus workload-specific IMC hardware.

Demonstrates the effectiveness of joint optimization in designing flexible IMC accelerators.

Abstract

Designing generalized in-memory computing (IMC) hardware that efficiently supports a variety of workloads requires extensive design space exploration, which is infeasible to perform manually. Optimizing hardware individually for each workload or solely for the largest workload often fails to yield the most efficient generalized solutions. To address this, we propose a joint hardware-workload optimization framework that identifies optimised IMC chip architecture parameters, enabling more efficient, workload-flexible hardware. We show that joint optimization achieves 36%, 36%, 20%, and 69% better energy-latency-area scores for VGG16, ResNet18, AlexNet, and MobileNetV3, respectively, compared to the separate architecture parameters search optimizing for a single largest workload. Additionally, we quantify the performance trade-offs and losses of the resulting generalized IMC hardware compared to workload-specific IMC designs.