Hardware-Software Co-optimised Fast and Accurate Deep Reconfigurable Spiking Inference Accelerator Architecture Design Methodology

TL;DR

This paper presents a hardware-software co-optimization approach for deep spiking neural networks, achieving near-accurate inference with reduced precision on a reconfigurable FPGA accelerator, enhancing energy efficiency and throughput.

Contribution

It introduces a novel co-optimization methodology for converting software-trained DNNs into efficient, accurate, reduced-precision SNNs on reconfigurable hardware.

Findings

Achieves within 1% accuracy of full-precision models with 8 spike timesteps.

Demonstrates FPGA implementation with 38.4 GOPS throughput at 1.54W.

Outperforms state-of-the-art efficiency metrics by 2-4.5x.

Abstract

Spiking Neural Networks (SNNs) have emerged as a promising approach to improve the energy efficiency of machine learning models, as they naturally implement event-driven computations while avoiding expensive multiplication operations. In this paper, we develop a hardware-software co-optimisation strategy to port software-trained deep neural networks (DNN) to reduced-precision spiking models demonstrating fast and accurate inference in a novel event-driven CMOS reconfigurable spiking inference accelerator. Experimental results show that a reduced-precision Resnet-18 and VGG-11 SNN models achieves classification accuracy within 1% of the baseline full-precision DNN model within 8 spike timesteps. We also demonstrate an FPGA prototype implementation of the spiking inference accelerator with a throughput of 38.4 giga operations per second (GOPS) consuming 1.54 Watts on PYNQ-Z2 FPGA. This corresponds to 0.6 GOPS per processing element and 2.25,GOPS/DSP slice, which is 2x and 4.5x higher utilisation efficiency respectively compared to the state-of-the-art. Our co-optimisation strategy can be employed to develop deep reduced precision SNN models and port them to resource-efficient event-driven hardware accelerators for edge applications.