SAIM: Scalable Analog Ising Machine for Solving Quadratic Binary Optimization Problems

TL;DR

This paper introduces a scalable CMOS-compatible analog Ising machine architecture using voltage-controlled oscillators and a novel tile design, enabling fast convergence for quadratic binary optimization problems.

Contribution

The paper proposes a new LHZ-based analog tile structure with oscillator circuits, demonstrating scalability and high-speed operation in 12nm technology.

Findings

Converges in about 31 ns

Operates at approximately 13 GHz

Demonstrates scalability in CMOS technology

Abstract

This paper presents a CMOS-compatible Lechner-Hauke-Zoller (LHZ)--based analog tile structure as a fundamental unit for developing scalable analog Ising machines (IMs). In the designed LHZ tile, the voltage-controlled oscillators are employed as the physical Ising spins, while for the ancillary spins, we introduce an oscillator-based circuit to emulate the constraint needed to ensure the correct functionality of the tile. We implement the proposed LHZ tile in 12nm FinFET technology using the Cadence Virtuoso. Simulation results show the proposed tile could converge to the results in about 31~ns. Also, the designed spins could operate at approximately 13~GHz.