LLC Intra-set Write Balancing
Keshav Krishna, Ayush Verma

TL;DR
This paper introduces a sample-based blocking technique for LLC in NVM systems to balance write traffic, reduce cell degradation, and extend memory lifespan without sacrificing performance.
Contribution
It proposes a novel sampling and history-based blocking method for LLC to improve write endurance in NVM, adaptable to various cache hierarchies.
Findings
Significantly balances write traffic in LLC.
Improves memory cell lifespan.
Maintains or improves system performance.
Abstract
The increasing use of Non-Volatile Memory (NVM) in computer architecture has brought about new challenges, one of which is the write endurance problem. Frequent writes to a particular cache cell in NVM can lead to degradation of the memory cell and reduce its lifespan. To solve this problem, we propose a sample-based blocking technique for the Last Level Cache (LLC). Our approach involves defining a threshold value and sampling a subset of cache sets. If the number of writes to a way in a sampled set exceeds the threshold, the way is blocked, and writes are redirected to other ways. We also maintain a history structure to record the number of writes in a set and a PC-Table to use for blocking in unsampled sets. Based on blocking on sampled sets, variance of values stored in history is used to determine whether blocking had a positive impact or not, and on this basis, value corresponding…
Peer Reviews
No public reviews on file for this paper yet. If you reviewed it on a platform where reviews are public (OpenReview, ICLR, NeurIPS, ICML), you can paste yours below so the community can read it here.
Videos
No videos yet. Explain this paper in a talk, walkthrough, or lecture? Add one.
Taxonomy
TopicsAssembly Line Balancing Optimization · Manufacturing Process and Optimization
