Per-Bank Bandwidth Regulation of Shared Last-Level Cache for Real-Time Systems
Connor Sullivan, Alex Manley, Mohammad Alian, Heechul Yun

TL;DR
This paper introduces a per-bank bandwidth regulation method for shared last-level caches in multicore real-time systems, enhancing performance and security against cache bank-aware DoS attacks.
Contribution
It proposes a novel per-bank bandwidth regulation approach that improves cache performance and system security in real-time multicore systems.
Findings
Protects real-time tasks from cache bank-aware DoS attacks.
Achieves up to 3.66× performance improvement for benign tasks.
Effectively prevents cache bank contention and improves throughput.
Abstract
Modern commercial-off-the-shelf (COTS) multicore processors have advanced memory hierarchies that enhance memory-level parallelism (MLP), which is crucial for high performance. To support high MLP, shared last-level caches (LLCs) are divided into multiple banks, allowing parallel access. However, uneven distribution of cache requests from the cores, especially when requests from multiple cores are concentrated on a single bank, can result in significant contention affecting all cores that access the cache. Such cache bank contention can even be maliciously induced -- known as cache bank-aware denial-of-service (DoS) attacks -- in order to jeopardize the system's timing predictability. In this paper, we propose a per-bank bandwidth regulation approach for multi-banked shared LLC based multicore real-time systems. By regulating bandwidth on a per-bank basis, the approach aims to prevent…
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Taxonomy
TopicsDistributed and Parallel Computing Systems · Real-Time Systems Scheduling · Advanced Data Storage Technologies
