Shavette: Low Power Neural Network Acceleration via Algorithm-level Error Detection and Undervolting

TL;DR

This paper presents a software-based method for enabling low-voltage operation in DNN accelerators, achieving significant energy savings without accuracy loss or extensive hardware modifications.

Contribution

It introduces an algorithm-level error detection approach that allows reduced voltage operation on off-the-shelf hardware, simplifying implementation and reducing costs.

Findings

18% to 25% energy savings on DNNs

No accuracy loss observed

Less than 3.9% throughput impact

Abstract

Reduced voltage operation is an effective technique for substantial energy efficiency improvement in digital circuits. This brief introduces a simple approach for enabling reduced voltage operation of Deep Neural Network (DNN) accelerators by mere software modifications. Conventional approaches for enabling reduced voltage operation e.g., Timing Error Detection (TED) systems, incur significant development costs and overheads, while not being applicable to the off-the-shelf components. Contrary to those, the solution proposed in this paper relies on algorithm-based error detection, and hence, is implemented with low development costs, does not require any circuit modifications, and is even applicable to commodity devices. By showcasing the solution through experimenting on popular DNNs, i.e., LeNet and VGG16, on a GPU platform, we demonstrate 18% to 25% energy saving with no accuracy loss of the models and negligible throughput compromise (< 3.9%), considering the overheads from integration of the error detection schemes into the DNN. The integration of presented algorithmic solution into the design is simpler when compared conventional TED based techniques that require extensive circuit-level modifications, cell library characterizations or special support from the design tools.