RapidStream IR: Infrastructure for FPGA High-Level Physical Synthesis

TL;DR

RapidStream IR is a flexible infrastructure for high-level physical synthesis of FPGA designs, enabling better physical optimization, portability, and extensibility, leading to significant frequency improvements across diverse applications.

Contribution

It introduces a novel intermediate representation that captures hierarchical interconnections and spatial info, facilitating reusable optimization passes and supporting diverse design sources and FPGA platforms.

Findings

Improves FPGA design frequency by 7% to 62%.

Supports integration of HLS, IPs, and RTL designs.

Demonstrates portability and extensibility through case studies.

Abstract

The increasing complexity of large-scale FPGA accelerators poses significant challenges in achieving high performance while maintaining design productivity. High-level synthesis (HLS) has been adopted as a solution, but the mismatch between the high-level description and the physical layout often leads to suboptimal operating frequency. Although existing proposals for high-level physical synthesis, which use coarse-grained design partitioning, floorplanning, and pipelining to improve frequency, have gained traction, they lack a framework enabling (1) pipelining of real-world designs at arbitrary hierarchical levels, (2) integration of HLS blocks, vendor IPs, and handcrafted RTL designs, (3) portability to emerging new target FPGA devices, and (4) extensibility for the easy implementation of new design optimization tools. We present RapidStream IR, a practical high-level physical synthesis (HLPS) infrastructure for representing the composition of complex FPGA designs and exploring physical optimizations. Our approach introduces a flexible intermediate representation (IR) that captures interconnection protocols at arbitrary hierarchical levels, coarse-grained pipelining, and spatial information, enabling the creation of reusable passes for design frequency optimizations. RapidStream IR improves the frequency of a broad set of mixed-source designs by 7% to 62%, including large language models and genomics accelerators, and is portable to user-customizable new FPGA platforms. We further demonstrate its extensibility through case studies, showcasing the ability to facilitate future research.