Mixed-precision finite element kernels and assembly: Rounding error analysis and hardware acceleration

TL;DR

This paper introduces a detailed rounding error analysis for mixed-precision finite element kernels, guiding hardware-accelerated implementations that are both fast and robust across various computational conditions.

Contribution

It provides the first fine-grained error analysis for mixed-precision FE kernels, including hardware acceleration strategies that maintain accuracy and improve performance.

Findings

Mixed-precision algorithms are up to 60 times faster than double precision.

The algorithms are accurate to the lower-precision unit roundoff, independent of problem conditioning.

First AMX-accelerated FE kernel implementations on Intel Sapphire Rapids CPUs.

Abstract

In this paper we develop the first fine-grained rounding error analysis of finite element (FE) cell kernels and assembly. The theory includes mixed-precision implementations and accounts for hardware-acceleration via matrix multiplication units, thus providing theoretical guidance for designing reduced- and mixed-precision FE algorithms on CPUs and GPUs. Guided by this analysis, we introduce hardware-accelerated mixed-precision implementation strategies which are provably robust to low-precision computations. Indeed, these algorithms are accurate to the lower-precision unit roundoff with an error constant that is independent from: the conditioning of FE basis function evaluations, the ill-posedness of the cell, the polynomial degree, and the number of quadrature nodes. Consequently, we present the first AMX-accelerated FE kernel implementations on Intel Sapphire Rapids CPUs. Numerical experiments demonstrate that the proposed mixed- (single/half-) precision algorithms are up to 60 times faster than their double precision equivalent while being orders of magnitude more accurate than their fully half-precision counterparts.