Using Intermittent Chaotic Clocks to Secure Cryptographic Chips

TL;DR

This paper explores the use of intermittent chaotic clocks generated from various chaotic maps to enhance the security of cryptographic chips against power analysis attacks, achieving low timing overhead and high resilience.

Contribution

It introduces a novel chaotic clocking scheme using optimized chaotic maps, notably the Ikeda map, to improve security with minimal timing overhead.

Findings

Chaotic clocks successfully protect against Correlation Power Analysis attacks.

Optimized Ikeda, Henon, and Logistic maps achieve lowest timing overhead.

Chaotic clocks approach the theoretical limit of half the execution time.

Abstract

This letter proposes using intermittent chaotic clocks, generated from chaotic maps, to drive cryptographic chips running the Advanced Encryption Standard as a countermeasure against Correlation Power Analysis attacks. Five different chaotic maps -- namely: the Logistic map, the Bernoulli shift map, the Henon map, the Tent map, and the Ikeda map -- are used in this work to generate chaotic clocks. The performance of these chaotic clocks is evaluated in terms of timing overhead and the resilience of the driven chip against Correlation Power Analysis attacks. All proposed chaotic clocking schemes successfully protect the driven chip against attacks, with the clocks produced by the optimized Ikeda, Henon, and Logistic maps achieving the lowest timing overhead. These optimized maps, due to their intermittent chaotic behavior, exhibit lower timing overhead compared to previous work. Notably, the chaotic clock generated by the optimized Ikeda map approaches the theoretical limit of timing overhead, i.e., half the execution time of a reference periodic clock.