Messaging-based Adaptive Vector Computing (MAVeC) Accelerator for AI Workloads

TL;DR

MAVeC is a messaging-based adaptive vector accelerator that improves AI workload performance by reducing data movement and orchestration overheads, achieving high utilization, lower latency, and significant throughput gains over traditional architectures.

Contribution

This paper introduces MAVeC, a novel messaging-driven execution model and hardware design for AI accelerators, enabling flexible, scalable, and efficient processing beyond compute-centric architectures.

Findings

Achieves over 97% array utilization across scales and problem sizes.

Delivers 5.8-6.1 TFLOPs/sec performance, outperforming TPU and NVIDIA H100 kernels.

Reduces end-to-end latency by 1.5-2x compared to traditional systolic arrays.

Abstract

The performance of AI accelerators is increasingly limited by data movement, memory access, and orchestration overheads rather than raw compute capability. This paper presents MAVeC, a messaging-based adaptive vector computing accelerator designed to support streaming execution and runtime configurability for AI workloads. MAVeC replaces centralized control with a message-driven execution model in which data and control propagate together across distributed hardware elements, enabling autonomous execution, flexible routing, and efficient coordination. We validate MAVeC's core hardware constructs and execution model using matrix multiplication and convolution workloads under a cycle-accurate, system-level ASIC design in TSMC 28 nm, capturing computation, communication, and reduction. MAVeC sustains greater than 97 percent array utilization across hardware scales and problem sizes by translating spatial capacity into effective computation. Once inputs are brought in, over 90 percent of communication remains on-chip through coordinated temporal reuse, spatial multicast, and on-fabric partial-sum reduction. On a 64x64 SiteO array, MAVeC sustains over 5 TFLOPs per second while reducing end-to-end latency. Compared to TPU-style systolic arrays and MEISSA under compute-centric models, MAVeC achieves 1.5-2x lower latency. When evaluated against optimized NVIDIA H100 FP32 kernels, MAVeC sustains 5.8-6.1 TFLOPs per second, delivering a consistent 6.0-7.2x throughput advantage across problem sizes. Energy results show that MAVeC converts higher instantaneous power into lower total energy by shortening execution time and amortizing data movement. These results demonstrate that message-driven execution provides an effective architectural foundation for overcoming data movement and orchestration bottlenecks, enabling scalable, high-utilization accelerators for future AI workloads.